1. Field of the Invention
This invention relates to a semiconductor memory and, more particularly, it relates to a semiconductor memory provided with a built-in voltage stress test mode capable of testing the voltage stress applied thereto.
2. Description of the Related Art
Conventionally, a normal access mode is used for a voltage stress test such as a burn-in test utilizing an accelerating voltage or temperature to be conducted on a dynamic type semiconductor memory (DRAM) in the course of manufacturing. Such a test is time consuming when a screening operation is carried out to a satisfactory extent by utilizing an accelerating voltage. This is because, while the memory cell transfer gate shows the largest electric field strength in the internal circuit of a DRAM, the duty ratio of the electric field at the transfer gate is too small in a normal operation mode of the device.
There have been proposed a couple of time saving burn-in test techniques respectively called a DC (direct current) burn-in test mode and an AC (alternating current) burn-in test mode in an attempt to reduce the time required for a burn-in test.
The former technique consists in applying a high voltage simultaneously to a plurality of word lines of the memory cell array of a DRAM in order to increase the duty ratio of the electric field at the memory cell transfer gate.
The latter technique, on the other hand, consists in dividing the word lines of the memory cell array of a DRAM into two groups, a group with odd numbers and another with even numbers, selecting either of them and applying a high voltage to the word lines of the selected group. Thus, a high voltage is applied to every other word line of the device. This technique is advantageous in that the insulation between adjacent word lines and bit lines can also be checked during the screening.
In an alternative technique of utilizing an AC burn-in test mode, every forth word line is selected by utilizing the row address counter for CBR (CAS before RAS) automatic refreshing while the DRAM is held under an operating condition so that it may be used even if the device is sealed in a package.
However, while the above described techniques can raise the duty ratio of the electric field applied to the word lines of a DRAM, the duty ratio at the transistor for the column selection lines and the column selection gate (DQ gate) connected thereto remains low.
Additionally, although the circuits peripheral to the memory cells can be screened in a reading operation by using a conventional screening technique, they cannot be screened in a writing operation. Thus, such a conventional technique of utilizing a burn-in test mode cannot by any means really make it a time saving test mode for a DRAM.
It should be particularly noted that, when minute transistors are used, the rate of occurrence of a defective insulation film given rise to by foreign fine particles (malfunctioning A mode) becomes high if compared with the rate of occurrence of malfunctioning mode due to insulation film destruction caused by a relatively strong electric field (malfunctioning B mode), meaning that defective devices cannot be satisfactorily removed by screening only the word lines to which a strong electric field is applied.
The above described column selection gate, column decoder and circuits peripheral to them can show a malfunctioning A mode due to a defective insulation film to a relatively high proportion. Thus, all the circuits with a low duty ratio have to be improved to show a high duty ratio in order for a burn-in test mode to make time saving in the real meaning of the word.
Meanwhile, in the generation of 64 MDRAMs, the time required for a strong electric field to be applied to the transfer gate differs by an order of 10-4 from the time required for a strong electric field to be applied to the peripheral circuit transistor. Nevertheless, a same insulation film is commonly used for both the peripheral circuit transistor and the cell transfer gate transistor.
Therefore, in the generation of 64 MDRAMs, while the insulation film for the transfer gate and the one for the peripheral circuit transistor are subjected to an electric field with different field strengths, it is quite probable that a defective insulation film, if any, may pass a series of initial screening tests if it is used for the cell transfer gate.
Additionally, when there is a great difference between the above mentioned duty ratios, the peripheral circuit having a large duty ratio might have been worn away by the time when the last initially defective insulation film of cell transfer gate is removed in a screening test.
Finally, the more insulation film is made thin, the more A mode malfunction may become dominant. Therefore, there inevitably arises a need that the duty ratio be raised to a certain level for all the circuits of a DRAM so that all the circuits may be subjected to screening tests under equal conditions not simply for B mode malfunction of the cell transfer gate that can be damaged when a strong electric field is applied thereto.
As pointed out above, conventional semiconductor memories are accompanied by the problem that they are not subjected to screening tests under equal conditions by raising the duty ratios of all the memory circuits in a voltage stress test.